Exemplary embodiments of the present invention relate to a semiconductor device and a fabricating method thereof, and more particularly, to an overlay vernier mask pattern of a semiconductor device, a formation method thereof, a semiconductor device including an overlay vernier pattern, and a formation method thereof.
In the fabrication process of a semiconductor integrated circuit, various processes such as masking, resist coating, etching, and stacking are performed. When performing the processes, a specific material layer may overlap a layer existing below the material layer, or may also be removed to prevent overlap from the material layer. In such a process, it is very important to appropriately align upper and lower process layers. In the fabrication process of a semiconductor device, registration is generally used for measuring the accuracy of inter-layer alignment. Registration is accomplished by allowing a matching pattern formed on an existing layer to overlap a distinct pattern distinguished from the matching pattern and comparing the position of the existing layer with the position of a subsequent layer. That is, by measuring the distance between an alignment mark of the subsequent layer and an alignment mark of the existing layer, misalignment between the two layers can be measured. A registration structure mainly used at the present time includes box-in-box overlay vernier, bar-in-bar overlay vernier, and the like.
However, as the integration degree of a semiconductor device increased, pitch between patterns is reduced. Patterns with a narrow pitch are not formed through a one-time photolithography process due to the limitation of a photolithography process. Rather, a dual patterning technology (DPT) has been used to form patterns with a narrow pitch by performing the photolithography process twice. The dual patterning technology is also applied to cases where, although patterns may be aligned in a peripheral circuit area with a relatively sufficient pitch, those patterns are not normally formed through a single photolithography. The dual patterning technology may also be applied to a cell area where predetermined type of patterns, for example, line and space type of patterns are aligned.
A process for forming a micro pattern by using the dual patterning technology will be briefly described below. First mask patterns are formed on a layer to be patterned through a first patterning process. A pitch between the first mask patterns is approximately twice as long as the pitch according to a design rule. Second mask patterns aligned between the first patterns are formed through a second patterning process. A lower layer to be patterned is etched through an etching process using the first mask patterns and the second mask patterns as etching masks, thereby forming micro patterns with the pitch according to the design rule. As described above, since the dual patterning technology forms mask patterns by performing a patterning process twice, a triple key is used in registration for checking alignment between upper and lower layers. That is, in the first patterning process for forming the first mask patterns, a first overlay vernier mask pattern for forming a first overlay vernier pattern is formed, and in the second patterning process for forming the second mask patterns, a second overlay vernier mask pattern is formed. An etching process is performed using the first overlay vernier mask pattern and the second overlay vernier mask pattern as etching masks, thereby forming first and second overlay vernier patterns. The first and second overlay vernier patterns are used as an outer bar and an overlay vernier pattern formed above through a subsequent process is used as an inner box, thereby recognizing an alignment relationship between upper and lower layers.
However, in such a process, an opening formed in the first overlay vernier mask pattern formed below may be covered by the second overlay vernier mask pattern formed above the first overlay vernier mask pattern. In such a case, although an etching process is performed using the first overlay vernier mask pattern and the second overlay vernier mask pattern as etching masks, the first overlay vernier pattern, which is to be formed by the first overlay vernier mask pattern, may not be formed. In addition, an opening formed in the second overlay vernier mask pattern may also overlap the first overlay vernier mask pattern formed below the second overlay vernier mask pattern. In such a case, since the first overlay vernier mask pattern serves as an etching barrier, the second overlay vernier pattern, which is to be formed by the second overlay vernier mask pattern, may not be normally formed.